1. Field of the Invention
The present invention relates to a data transfer method and electronic device and, more particularly, to a data transfer method and electronic device whereby data is sequentially transferred to a plurality of cascade-connected semiconductor integrated circuits.
2. Description of the Related Art
Liquid crystal display devices are used as dot matrix-type display devices in a variety of devices such as personal computers based on the merits of their thin form, light weight, and low power, with active matrix-type color liquid crystal display devices, which are useful in controlling images in particular highly accurately, holding the mainstream.
A liquid crystal display module of a liquid crystal display device comprises a liquid crystal panel (LCD panel), a control circuit (referred to as a ‘controller’ hereinbelow) consisting of a semiconductor integrated circuit device (referred to as an ‘IC’ hereinbelow), a scan-side driver circuit (referred to as a ‘scan driver’ hereinbelow) and a data-side driver circuit (referred to as a ‘data driver’ hereinbelow). The scan driver and the data driver consist of an IC. In many cases, a plurality of data drivers is provided, for example, in a case where the liquid crystal panel resolution is XGA (1024×768 pixels: one pixel is made up of three dots of R (red), G (green), and B (blue)) and in the case of a 262144 color display (R, G, and B each have 64 grayscales), there is an arrangement of eight data drivers, where a single data driver is assigned the display of 128 pixels. Here, it is necessary to run wiring outside the data driver in order to transfer display data, a timing signal, and so forth from the controller to each data driver. Therefore, area for the layout is required. Therefore, in order to keep the layout as small as possible, as a system for transferring display data, a timing signal, and so forth from the controller to each data driver, the cascade system, in which a transfer is made from the controller only to an initial-stage data driver and sequentially via an IC as per the start signal transfer method of the prior art to data drivers of a second-stage and subsequent stages (referred to as the ‘interchip transfer system’ hereinbelow) is employed (See Japanese Patent No. 3416045, for example).
On the other hand, in the case of a signal transfer between ICs within a liquid crystal display module, a CMOS interface, which constitutes means for transmitting a twin-value voltage signal the amplitude of which changes between the supply voltage (“H” level) and ground (“L” level), is employed according to the prior art. As the detail and size of the image of the liquid crystal panel increases, the number of pixels of the liquid crystal panel also increases, and there has also be an expansion in the marketplace from XGA to SXGA (1280×1024 pixels) and to UXGA (1600×1200 pixels). Accordingly, the clock frequency corresponding to the liquid crystal panel is, in the case of XGA, currently about 60 MHz but is a higher clock frequency for SXGA and above. Although high-speed transfers of clock signals, display data, and so forth are required between the controller and data drivers within a liquid crystal display module, there has been the problem that, in the case of a conventional CMOS interface, the number of wires increases when the parallel transmission system must be adopted in order to prevent EMI (Electromagnetic Interference) noise.
Accordingly, in order to resolve the above problem for XGA and above, an interface of a small-amplitude differential signal transmission system has been used. As a representative example, an interface of the RSDS (Reduced Swing Differential Signaling: registered trademark of National Semiconductor) system (referred to as an ‘RSDS interface’ hereinbelow) has been used (See Japanese Patent No. 3285332).
Further, in cases where an RSDS interface is used in the above interchip transfer of display data, a timing signal, and so forth, although the EMI noise between the controller and the initial-stage data driver is reduced, the display data and clock signal must be transferred to the second data driver and subsequent data drivers at the same frequency. However, because the length of the wiring on the glass substrate between the data drivers is long in comparison with the length of the wiring on the glass substrate that governs the impedance (mainly resistance) of the wiring between the controller and the initial-stage data driver, the wiring resistance between the data drivers is large in comparison with the wiring resistance between the controller and the initial-stage data driver and, hence, the setup/hold margin when display data is captured at the edge of the clock signal by means of the data drivers of the second and subsequent stages is reduced, meaning that there is the risk that the display data cannot be captured accurately. Further, in cases where an RSDS interface is used in the transfer of display data between data drivers, there is the problem that a fixed current must flow in order to transmit the RSDS signal and the current consumption is large.